In development of a semiconductor device, particularly a semiconductor storage device, ever finer patterning is developed for memory cells to achieve larger capacities and lower costs. In a semiconductor storage device mounted with a floating gate structure such as a NAND nonvolatile semiconductor memory device, the wire pitch between word lines to be a control gate in a gate portion is made ever finer. Such finer patterning of LSIs is actively promoted to achieve performance improvement such as a faster operation and lower power consumption of elements due to higher integration and the reduction in manufacturing costs. In recent years, flash memories in minimum processing dimensions of, for example, 20 nm or so have been in mass production and still finer patterning and increasing technical difficulty are expected in the future.
A NAND nonvolatile semiconductor memory device capable of electrically rewriting data stores data by changing the amount of charge of the floating gate of a cell transistor to change the threshold voltage thereof. In general, electrons are emitted and injected between the floating gate and a semiconductor substrate via a gate dielectric film. The amount of charge of the floating gate is thereby controlled. However, various problems arise as finer circuit patterning is promoted in response to requests of finer patterning in recent years.
As a limit of finer patterning of a memory cell, a problem of difficulty of embedding a control gate between adjacent floating gates is known because the physical thickness of an IPD (Inter Poly Dielectric) film cannot be made thinner and the space between floating gates adjacent in an element isolation direction is filled with the IPD film. In addition, even if the control gate is embedded, a problem arises that the width thereof is too thin to function as an electrode. As a solution to such problems, for example, changing the polarity of a floating gate from the n type to the p type is attempted. In an n-type floating gate, the charge holding capability is not sufficient because electrons accumulate in an IPD film interface or a tunnel dielectric film of the floating gate after writing. In a p-type floating gate, by contrast, electrons recombine with holes after writing and no electron is present in the conduction band and thus, the charge holding capability thereof is considered to be superior. Therefore, the thickness of a tunnel dielectric film can be made thinner and when the same coupling ratio is maintained, the height of a floating gate can be decreased and the IPD dielectric film can be made thinner. Because carriers are injected into a p-type floating gate during a write operation, in addition to being a thin tunnel dielectric film, the write operation can be performed at a lower voltage. Accordingly, a leak current of the IPD dielectric film can also be reduced. Therefore, the aspect ratio can be decreased by adopting a p-type floating gate to make the thickness of an IPD film thinner or reduce the height of the floating gate so that still finer cells can be formed.
However, if a p-type floating gate is adopted, when a p-type impurity is doped, a problem arises that not only a memory cell region in which a floating gate is formed, but also a region of peripheral circuits such as a resistance element where the n-type polarity is desirable is similarly doped with the p-type impurity.